[Verilog] ISEエラー：HDLCompiler：806

Question

ISEでは以下のエラーが発生しており、実際の問題を把握することはできません。誰にも手がかりはありますか？

エラーメッセージ：

ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 29: Syntax error near "posedge". 
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 39: Syntax error near "<=". 
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 43: Syntax error near "<=". 
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 47: Syntax error near "<=". 
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 50: Syntax error near "end". 
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 54: Syntax error near "posedge". 
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 64: Syntax error near "<=". 
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 68: Syntax error near "<=". 
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 72: Syntax error near "<=". 
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 75: Syntax error near "end". 
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 88: Syntax error near "posedge". 
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 98: Syntax error near "<=". 
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 102: Syntax error near "<=". 
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 106: Syntax error near "<=". 
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 109: Syntax error near "end". 
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 113: Syntax error near "posedge". 
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 123: Syntax error near "<=". 
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 127: Syntax error near "<=". 
ERROR:HDLCompiler:806 - "C:\Users\Ray\Documents\project\QFC\QFC_A.v" Line 131: Syntax error near "<=". 

、ここでは私のコードです：

`timescale 1ns/1ps 

module QFC_A # 
(
    parameter SPI_CYCLE = 100000, 
    parameter MASTER_ID = 8'h66, 
    parameter SLAVE_ID = 8'h66 
) 

(
    input i_axi_lite_s_aclk, 
    input i_rst, 
    input i_din, 
    output o_en, 
    output o_dout 
); 



reg [255:0] r_frame_message; 
reg [3:0] r_cnt_message; 
wire [31:0] w_frame_word_message; 
wire w_message_rd_en; 
wire w_id_match_message; 
wire w_message_empty; 
wire w_message_ready; 


always @ (posedge i_axi_lite_s_aclk & posedge i_rst) 
    begin 
     if (i_rst) 
      begin 
       r_frame_message <= 256'h0; 
      end 
     else 
      begin 
       if (w_id_match_message & (r_cnt_message != 4'hf)) 
        begin 
        r_frame_message <= {224'h0, w_frame_word_message}; 
        end 
       else if (w_message_rd_en & w_message_empty) 
        begin 
         r_frame_message <= 256'h0; 
        end 
       else if (w_message_rd_en) 
        begin 
         r_frame_message <= {r_frame_message[223:0], w_frame_word_message}; 
        end 
      end 
    end 

assign w_id_match_message = (w_frame_word_message[23:16] == MASTER_ID)? 1'b1 : 1'b0; 

always @ (posedge i_axi_lite_s_aclk & posedge i_rst) 
    begin 
     if (i_rst) 
      begin 
       r_cnt_message <= 4'h0; 
      end 
     else if (w_message_rd_en) 
      begin 
       if (w_id_match_message) 
        begin 
         r_cnt_message <= 4'h0; 
        end 
       else if (r_cnt_message == 4'hf) 
        begin 
         r_cnt_message <= 4'h0; 
        end 
       else 
        begin 
         r_cnt_message <= r_cnt_message + 4'h1; 
        end 
      end 
    end 

assign w_message_ready = (r_cnt_message == 4'hf & ~w_send_ready)? 1'b1 : 1'b0; 

reg [255:0] r_frame_data; 
reg [3:0] r_cnt_data; 
wire [31:0] w_frame_word_data; 
wire w_data_rd_en; 
wire w_id_match_data; 
wire w_data_empty; 
wire w_data_ready; 


always @ (posedge i_axi_lite_s_aclk & posedge i_rst) 
    begin 
     if (i_rst) 
      begin 
       r_frame_data <= 256'h0; 
      end 
     else 
      begin 
       if (w_id_match_data & (r_cnt_data != 4'hf)) 
        begin 
         r_frame_data <= {224'h0, w_frame_word_data}; 
        end 
       else if (w_data_rd_en & w_data_empty) 
        begin 
         r_frame_data <= 256'h0; 
        end 
       else if (w_data_rd_en) 
        begin 
         r_frame_data <= {r_frame_data[223:0], w_frame_word_data}; 
        end 
      end 
    end 

assign w_id_match_data = (w_frame_word_data[23:16] == MASTER_ID)? 1'b1 : 1'b0; 

always @ (posedge i_axi_lite_s_aclk & posedge i_rst) 
    begin 
     if (i_rst) 
      begin 
       r_cnt_data <= 4'h0; 
      end 
     else if (w_data_rd_en) 
      begin 
       if (w_id_match_data) 
        begin 
         r_cnt_data <= 4'h0; 
        end 
       else if (r_cnt_data == 4'hf) 
        begin 
         r_cnt_data <= 4'h0; 
        end 
       else 
        begin 
         r_cnt_data <= r_cnt_data + 4'h1; 
        end 
      end 
    end 

assign w_data_ready = (r_cnt_data == 4'hf & ~w_send_ready)? 1'b1 : 1'b0;  

reg [255:0] r_frame_rec; 
reg [3:0] r_cnt_rec; 
wire[31:0] w_frame_word_rec; 
wire w_rec_en; 
wire w_id_match_rec; 
wire w_rec_ready; 
wire w_rec_success; 

always @ (posedge i_axi_lite_s_aclk & posedge i_rst) 
    begin 
     if (i_rst) 
      begin 
       r_frame_rec <= 256'h0; 
      end 
     else 
      begin 
       if (w_id_match_rec & (r_cnt_rec != 4'hf)) 
        begin 
         r_frame_rec <= {224'h0, w_frame_word_rec}; 
        end 
       else if (w_rec_en) 
        begin 
         r_frame_rec <= {r_frame_rec[223:0], w_frame_word_rec}; 
        end 
      end 
    end 

assign w_id_match_rec = (w_frame_word_rec[23:16] == SLAVE_ID)? 1'b1 : 1'b0; 

always @ (posedge i_axi_lite_s_aclk & posedge i_rst) 
    begin 
     if (i_rst) 
      begin 
       r_cnt_rec <= 4'h0; 
      end 
     else if (w_rec_en) 
      begin 
       if (w_id_match_rec) 
        begin 
         r_cnt_rec <= 4'h0; 
        end 
       else if (r_cnt_rec == 4'hf) 
        begin 
         r_cnt_rec <= 4'h0; 
        end 
       else 
        begin 
         r_cnt_rec <= r_cnt_rec + 4'h1; 
        end 
      end 
    end 

assign w_rec_ready = (r_cnt_rec == 4'hf)? 1'b1 : 1'b0;  
assign w_rec_success = ((w_rec_ready) & (r_frame_rec[251] == 1'b1) & (checksum(r_frame_rec[239:16]) == r_frame_rec[15:0]))? 1'b1 : 1'b0;  

reg [2:0] r_current_state; 
reg [2:0] r_next_state; 
reg [16:0] r_cycle_timer; 
reg [14:0] r_trans_timer; 
reg [1:0] r_cycle_s; 
reg [223:0] r_payload; 
reg [255:0] r_frame_send; 
wire w_cycle; 
wire w_cycle_pos; 
wire w_state_start; 
localparam IDLE   = 3'h0; 
localparam SEND_MSG  = 3'h1; 
localparam RESEND_MSG = 3'h2; 
localparam SEND_DATA  = 3'h3; 
localparam RCG_ACK  = 3'h4; 
localparam CHANGE_TLG = 3'h5; 
localparam ABORT_MSG  = 3'h6; 

always @ (posedge i_axi_lite_s_aclk & posedge i_rst) 
    begin 
     if (i_rst) 
      begin 
       r_cycle_timer <= 16'h0; 
      end 
     else if (r_cycle_timer < SPI_CYCLE) 
      begin 
       r_cycle_timer <= r_cycle_timer + 16'h1; 
      end 
     else 
      begin 
       r_cycle_timer <= 16'h0; 
      end 
    end 

assign w_cycle = (r_cycle_timer == SPI_CYCLE)? 1'b1 : 1'b0; 

always @ (posedge i_axi_lite_s_aclk & posedge i_rst) 
    begin 
     if(i_rst) 
      begin 
       r_cycle_s <= 2'h0; 
      end 
     else 
      begin 
       r_cycle_s <= {r_cycle_s[0], w_cycle}; 
      end 
    end 

assign w_cycle_pos = (~r_cycle_s[1] & r_cycle_s[0]); 


function reg [15:0] checksum (input reg [223:0] r_frame) 
    begin 
     integer i; 
     reg [15:0] r_sum_1; 
     reg [15:0] r_sum_2; 

     r_sum_1 = 16'hff; 
     r_sum_2 = 16'hff; 
     for (i = 0; i < 28; i++) 
      begin 
       r_sum_1 = r_sum_1 + r_frame[(223-8*i)-:8]; 
       r_sum_2 = r_sum_1 + r_sum_2; 
       if (i == 20) 
        begin 
         r_sum_1 = (r_sum_1 >> 8) + (r_sum_1 & 8'hff); 
         r_sum_2 = (r_sum_2 >> 8) + (r_sum_2 & 8'hff); 
        end 
      end 
     r_sum_1 = (r_sum_1 >> 8) + (r_sum_1 & 8'hff); 
     r_sum_2 = (r_sum_2 >> 8) + (r_sum_2 & 8'hff); 
     r_sum_1 = (r_sum_1 >> 8) + (r_sum_1 & 8'hff); 
     r_sum_2 = (r_sum_2 >> 8) + (r_sum_2 & 8'hff); 
     checksum = (r_sum_1 << 8) | r_sum_2; 
    end 
endfunction 



always @ (*) 
    begin 
     case (r_current_state) 
      IDLE:    begin 
            r_next_state = SEND_DATA; 
            r_frame_send = {8'h90, MASTER_ID, 240'h0}; 
           end 
      SEND_MSG:   begin 
            r_next_state = RCG_ACK; 
            if (w_state_start) 
             begin 
              w_message_rd_en = 1'b1; 
              w_send_ready = 1'b0; 
              w_state_start = 1'b0; 
             end 
            if (r_frame_message == 256'h0) 
             begin 
              w_message_rd_en = 1'b0; 
              r_frame_send = {r_frame_send[], MASTER_ID, 240'h0}; 
             end 
            else if 
           end 
      RCG_ACK:   begin 
            if (w_rec_success) 
             begin 
              r_next_state = CHANGE_TLG; 
             end 
            else if (r_resend_cnt == 2'b11) 
              begin 
               r_next_state = ABORT_MSG; 
              end 
           end 
     endcase 
    end 

endmodule 

Answer 1

このエラーの原因としては、@ (posedge i_axi_lite_s_aclk & posedge i_rst)で&からです。それは不正な構文であり、パーサーを混乱させていると推測しています。ノンブロッキング代入（<=）でエラーが表示されます。 &をorに変更してください（IEEE 1364-2001は感度リストのセパレータとして,もサポートしていますが、LRMを有効にしていないと思います）。

例：@ (posedge i_axi_lite_s_aclk or posedge i_rst)

他の構文エラーがたくさんあります。関数のヘッダーにセミコロンがない、else ifがぶら下がっている、宣言されていない識別子など。私はあなたのためにそれらを修正するつもりはありません。

_FYI：

&論理オペレータ&&次いで異なり、ビット単位のAND演算子です。あなたは&&が推奨される場所で&を使用しています。論理演算子とビット演算子の違いを調べることをお勧めします。

? :を使用する多くのシンセサイザでは、明示的な2対1マルチプレクサが作成されます。 ? :を使用するすべてのケースで、選択値は出力値と同じです。だから、スペースを無駄にしているだけかもしれません。

assign w_message_ready = (r_cnt_message == 4'hf & ~w_send_ready)? 1'b1 : 1'b0;をassign w_message_ready = (r_cnt_message == 4'hf && !w_send_ready);に変更することをお勧めします。機能的には同じですが、後者はより明確で簡潔です。